Analog circuits including analog integrated circuit amplifiers are common components in many electronic devices. As electronic devices are desired to be portable and small, analog integrated circuit amplifiers are desired to be formed with low area and to be operated with low power consumption.
For minimizing current dissipation, an adaptive biasing amplifier increases biasing currents depending on the input. FIG. 1 shows a circuit diagram of a prior art adaptive biasing amplifier 100 as disclosed in Degrauwe et al. “Adaptive Biasing CMOS Amplifier”, IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 3, pages 522-528, June 1982.
Referring to FIG. 1, the adaptive biasing amplifier 100 includes NMOSFETs (N-channel metal oxide semiconductor field effect transistors) MN1 and MN2 having gates with inputs Vin− and Vin+ applied thereon, respectively. In addition, diode connected PMOSFETs (P-channel metal oxide semiconductor field effect transistors) MP1 and MP2 are respectively connected to drains of the NMOSFETs MN1 and MN2. The sources of the NMOSFETs MN1 and MN2 are connected to a static current source ISS.
The adaptive biasing amplifier 100 also includes a first pair of NMOSFETs MN3 and MN4 forming a first current mirror, a second pair of NMOSFETs MN5 and MN6 forming a second current mirror, a third pair of NMOSFETs MN7 and MN8 forming a third current mirror, and a fourth pair of NMOSFETs MN9 and MN10 forming a fourth current mirror. The NMOSFETs MN5 and MN6 have area scaling with a ratio of 1:A, respectively, and the NMOSFETs MN7 and MN8 have area scaling with a ration of A:1, respectively.
PMOSFETs MP3 and MP4 have gates connected to the gate of the PMOSFET MP1, and PMOSFETs MP5 and MP6 have gates connected to the gate of the PMOSFET MP2. The PMOSFETs MP3, MP4, MP5, and MP6 are connected to the current mirrors formed by the NMOSFETs MN3, MN4, MN5, MN6, MN7, MN8, MN9, and MN10.
In addition, the PMOSFETs MP3, MP4, MP5, and MP6 have sources connected to a high supply voltage VDD, and the NMOSFETs MN3, MN4, MN5, MN6, MN7, MN8, MN9, and MN10 have sources connected to a low supply voltage VSS which may be the ground voltage. As a difference between the inputs Vin− and Vin+ increases, the NMOSFETs MN3, MN4, MN5, MN6, MN7, MN8, MN9, and MN10 and the PMOSFETs MP3, MP4, MP5, and MP6 increase the respective biasing currents through the MOSFETs MN1, MN2, MP1, and MP2.
The adaptive biasing amplifier 100 has numerous current mirrors formed by the NMOSFETs MN3, MN4, MN5, MN6, MN7, MN8, MN9, and MN10 and numerous static current paths formed by the PMOSFETs MP3, MP4, MP5, and MP6. Such components dissipate relatively high static current resulting in low current efficiency. In addition, the input NMOSFETs MN1 and MN2 have diode-connected loads MP1 and MP2 resulting in low GBW (gain bandwidth).
FIG. 2 shows a circuit diagram of another prior art adaptive biasing amplifier 110 as disclosed in Callewaert et al. “Class AB CMOS Amplifiers with High Efficiency”, IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, pages 684-691, June 1990. The adaptive biasing amplifier 110 includes input NMOSFETs MN11 and MN12 and sensing NMOSFETs MN13 and MN14. Such NMOSFETs MN11, MN12, MN13, and MN14 have gates with inputs Vin− and Vin+ applied thereon as illustrated in FIG. 2.
Also in FIG. 2, a first static current source ISS1 is connected to the source of the NMOSFET MN14, and a second static current source ISS2 is connected to the source of the NMOSFET MN13. The adaptive biasing amplifier 110 also includes a pair of NMOSFETs MN15 and MN16 forming a first current mirror and another pair of NMOSFETs MN17 and MN18 forming a second current mirror. The NMOSFETs MN15 and MN16 have area scaling with a ratio of 1:A, respectively, and the NMOSFETs MN17 and MN18 have area scaling with a ratio of A:1, respectively.
A pair of PMOSFETs MP11 and MP12 forms a third current mirror connected between a high supply voltage VDD and the NMOSFETs MN11 and MN14. A pair of PMOSFETs MP13 and MP14 forms a fourth current mirror connected between the high supply voltage VDD and the NMOSFETs MN13 and MN12. A first bias current source Ib1 is connected between the high supply voltage VDD, the drain of the NMOSFET MN11, and a source of a biased PMOSFET MP15. Further referring to FIG. 2, PMOSFETs MP17′ and MP18′ that are diode-connected and an NMOSFET MN19′ are formed for biasing the gate of the PMOSFET MP15. The PMOSFET MP15 has a drain connected to the drain of the NMOSFET MN15.
A second bias current source Ib2 is connected between the high supply voltage VDD, the drain of the NMOSFET MN12, and a source of another biased PMOSFET MP16. A drain of the PMOSFET MP16 is connected to a drain of the NMOSFET MN18. Two diode-connected PMOSFETs MP17 and MP18 are connected between the high supply voltage VDD and an NMOSFET MN19. The gate of the PMOSFET MP16 is connected to the gate of the PMOSFET MP18. The gate of the NMOSFET MN19 is connected to the gate of the NMOSFET MN18. The NMOSFETs MN15, MN16, MN17, MN18, and MN19 have sources connected to a low supply voltage VSS which may be the ground voltage.
As a difference between the input voltages Vin− and Vin+ increases, the components in the adaptive biasing amplifier 110 of FIG. 2 increase the respective biasing currents through the MOSFETs MN11, MN12, MP11, and MP14. In addition, the GBW (gain bandwidth) of the adaptive biasing amplifier 110 of FIG. 2 is improved from the adaptive biasing amplifier 100 of FIG. 1.
However, the first series of diode-connected PMOSFETs MP17 and MP18 and the second series of diode-connected PMOSFETs MP17′ and MP18′ result in increased operating voltage in the adaptive biasing amplifier 110 that consequently has a limited minimum operating voltage. Lower operating voltage is desired for minimizing power consumption and portability with a lighter battery. In addition, the adaptive biasing amplifier 110 of FIG. 2 includes four current sources ISS1, ISS2, Ib1, and Ib2 that occupy large integrated circuit area.
Thus, adaptive biasing amplifiers are desired to have high GBW (gain bandwidth), minimized area, high current efficiency, and low operating voltage.